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W25Q64DW
11.7 AC Electrical Characteristics ( cont’d)
SPEC
DESCRIPTION
SYMBOL
ALT
MIN
TYP
MAX
UNIT
/HOLD Active Hold Time relative to CLK
/HOLD Not Active Setup Time relative to CLK
/HOLD Not Active Hold Time relative to CLK
t CHHH
t HHCH
t CHHL
5
5
5
ns
ns
ns
/HOLD to Output Low-Z
/HOLD to Output High-Z
Write Protect Setup Time Before /CS Low
Write Protect Hold Time After /CS High
/CS High to Power-down Mode
/CS High to Standby Mode without Electronic
t HHQX (2)
t HLQZ (2)
t WHSL (3)
t SHWL (3)
t DP (2)
t RES 1 (2)
t LZ
t HZ
20
100
7
12
3
30
ns
ns
ns
ns
μs
μs
Signature Read
/CS High to Standby Mode with Electronic Signature
t RES 2 (2)
30
μs
Read
/CS High to next Instruction after Suspend
/CS High to next Instruction after Reset
t SUS (2)
t RST (2)
20
30
μs
μs
Write Status Register Time
Byte Program Time (First Byte) (4)
Additional Byte Program Time (After First Byte) (4)
Page Program Time
Sector Erase Time (4KB)
Block Erase Time (32KB)
Block Erase Time (64KB)
Chip Erase Time
t W
t BP1
t BP2
t PP
t SE
t BE 1
t BE 2
t CE
10
20
2.5
0.7
30
120
150
15
15
50
10
3
200/400 (5)
800
1,000
60
ms
μs
μs
ms
ms
ms
ms
s
Notes:
1.
2.
3.
4.
5.
Clock high + Clock low must be less than or equal to 1/f C .
Value guaranteed by design and/or characterization, not 100% tested in production.
Only applicable as a constraint for a Write Status Register instruction when SRP[1:0]=(0,1).
For multiple bytes after first byte within a page, t BPN = t BP1 + t BP2 * N (typical) and t BPN = t BP1 + t BP2 * N (max), where N =
number of bytes programmed.
Max Value t SE with <50K cycles is 200ms and >50K & <100K cycles is 400ms.
Publication Release Date: September 18, 2012
- 73 -
Revision D
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